The present invention relates to semiconductor technology, and more particularly to an MOS transistor, MOS integrated circuit device, and manufacturing method for reducing coupling capacitance between a gate electrode and source/drain electrodes.
Metal oxide semiconductor field effect transistor devices (MOSFETs) formed in a semiconductor substrate are widely used in integrated circuit devices (ICs). Typically, a FET transistor device includes a gate structure configured to form a channel region, and a source region and a drain region disposed on opposite sides of the channel region. The gate structure, the source and drain regions are connected to associated terminals that are disposed on the same side of the semiconductor substrate.
As technology nodes shrink in IC designs, transistor devices are continuously getting smaller, the spacing between the gate electrodes, and the source/drain electrodes continues to decrease, resulting in an increase of coupling capacitance between the gate and source/drain electrodes. Because the contacts openings of the source and drain electrodes and the gate contact opening disposed between them are disposed on the same side of the semiconductor substrate, such structures increase the coupling capacitance between the gate electrode and the source/drain electrodes.
The increase in coupling capacitance between the gate and source/drain electrodes adversely affects the performance of a transistor device, which, in turn, affects the performance of an integrated circuit device having such a transistor device. While the prior art fin-type field effect transistor (Fin FET) may somewhat reduce coupling capacitive effects, however, as feature sizes continue to shrink, conventional techniques may become inefficient in reducing coupling capacitance between gate and source/drain electrodes.
Therefore, it would be beneficial, both to circuit and device performance and to manufacturing economies, if the source/drain electrodes were to be placed on an opposite side of the gate electrode to reduce coupling capacitance.